Performance Analysis of an Efficient Router using X Y Algorithm

As more and functions are expected to be performed by a single electronic device (such as smartphone, smart television, etc.), the need have components on SoC is increasing, posing new difficulties for NoC. The majority of NoC designs utilise mesh, torus, or other topologies ensure robust router. Most solutions, however, fall short when it comes addressing key issues like throughput, area overhead, latency, well QoS congestion. current paper proposes concept reconfigurable router that can used in No C settings. For suggested router's design, we use Verilog, formal language describing hardware (Verilog HDL). four-channel presented here has an east-west-north-south orientation crossbar switch connecting two pairs channels. Each channel consists multiplexer FIFO buffer. input output handled multiplexers, data stored buffers. architectures south developed initially. Afterwards remaining three channels made. Routers channels, buffers, switches their overall design. Simulating proposed design Modelsim obtaining RTL view Xilinx ISE 14.0 primary methods approaching this problem. power consumption greatly reduced employing Power gating technique.. XPower Analyzer application determine total power. demonstrated findings obtained, uses less energy than conventional routers.